1. Technical Field
The present invention relates generally to digital interface circuits, and more particularly, to circuits and systems that evaluate data jitter.
2. Description of the Related Art
Data jitter determination is necessary to evaluate the performance of high-speed interface components and interfaces, as well as other circuits where jitter affect the bit error rate (BER). Determining data jitter is also desirable in many circuits that determine the quality of a received or transmitted data signal that also adapt performance of an interface in order to accommodate or reduce a level of data signal jitter.
In laboratory environments, high-accuracy laboratory instruments may be used to determine the jitter of a signal via very stable reference clocks and long integration times. However, the challenge of probing a very high frequency data signal and/or high-impedance data signal is significant, as the effects of the probe must be accounted for in the measurements and probe characteristics can vary over time and the probe compensation model may not be accurate under actual measurement conditions. Further, significant circuit area can be consumed in the impedance-matched and isolated output pads that permit such precision measurements. Such equipment is expensive and it is typically unfeasible to incorporate the equivalent of such instrumentation within production circuits.
On-chip measurements of data jitter are either performed using an internal global clock or an external sample clock with an internal delay line. Use of the internal global clock is limited in that clock jitter and data jitter cannot be separated. When an external sample clock is used, the delay accuracy, and thus the accuracy of the jitter measurement, is difficult to control. Since one inverter delay is typically the shortest delay available for fabricating an internal delay line, the resolution of the jitter measurement is then limited to one inverter delay. When measuring the jitter level of low-jitter signals, the resolution of the delay line technique is insufficient for accurate results. Further, if a large delay range is provided, the area and power required can be quite large, since the delay is typically operating at a very high clock frequency.
It is therefore desirable to provide a method and apparatus for determining data signal jitter that is low cost, can be at least partially integrated in a production circuit with no probing error and can quickly determine the jitter level of a data signal.